ADC parameter understanding

ADC - Analog to digital converter

1. Resolution: no. of bits (8/10/12/... bits)
2. Input clock frequency (MHz)
3. Pre scalar
4. Sampling frequency
5. Channels
6. Single / Differential channel
7. Vref (Reference voltage)
8. VDD (Supply voltage)

Example: if input locking frequency for ADC is 18MHz

Prescalar values varying from 1, 2, 4, 8 to 64

Clock frequency = Input clock frequency / Prescalar

Sampling frequency = Clock Frequency / No. of clock required for single conversion

No. of clock required for single conversion = No. of bits + x

x = varies from ADC to ADC. But is usually 3 to 5 bits

So, in our case, if its a 12-bit ADC and x=6 and prescalar = 1

then, 

Clock frequency  = 18MHz;

Sampling frequency = 18MHz/18 = 1Msps (1 mega samples per second)

EOC (End of conversion) line signal is present in each ADC and can be used as interrupt for ADC ISR.

If no of channels are more, then Time required for signal conversion further increases. In our case, if 8-channels are used, then

Conversion frequency = Sampling frequency / No. of channels

Resolution is achieved over the 0V to Vref range

Vref max limit = VDD

Usually minimum limit is also mentioned (Eg. 1.1V)

Successive Approximation Register(SAR) ADC:

In SAR, register of bits equal to no. of bits of ADC is used.

By using binary search pattern, it goes through all bits toggling from MSB to LSB and providing digital input to internal DAC. DAC generates the Analog voltage respectively which is used to compare with the input analog signal at the analog comparator stage. Sampled value is held until the complete conversion process is not complete. Once the conversion is complete, EOC signal is generated.

Voltage step = Vref / 2 ^ No. of adc bits

Hence,

Quantisation error range = +/- (Voltage step / 2)

ADC types:

1. Successive approximation ADC (Sample and Hold type)
2. Sigma delta ADC

DAC types:

1. R-2R ladder

Sample and Hold (S/H) OR Track and Hold:
These are usually used for high conversion rate (i.e. high Msps) application. There are two steps in SAR ADC.: Sample and Conversion.

SAR ADC goes through following states for every iteration:

1. Track mode: Here the output signal follows the input signal. "Slew rate" defines the signal following characteristic of the sampling capacitor.
2. Track to Hold mode: Here the input is captured and kept constant. "Transient Settling Time" is an important parameter to onsider. Usually it is mentioned as "Sample time (ts)" in datasheet.
3. Hold mode: Now the charge on the Capacitor Ch is held almost constant, during the conversion to digital value n-bit. Here, "Droop rate" is important parameter. It defines the charge holding capacity of the smapling capacitor.
4. Hold to Track mode: Here the output signal starts following the input signal. "Acquisition Time" defines the time required for output signal to start following the input signal.

Hence, min. time for whole sample and hold cycle  (Tconv)=

Min.Sample time (Transient Settling time) + Approximation time + Acquisition Time

Max. sampling rate = 1/ Tconv

 - Sampling time is adjustable.

 - ADC clock frequency is usually variable

 - Hence, sampling rate (Ksps/ Msps) can be varied.

Manufacturers:

Most of the applications require ADC along with the processor to process the data.

There are requirements to fit these in small space. So usually we look for a MCU with good ADC functionality. In these cases, as per my experience, ST Microelectronics (STM32F302RB) provides the best solutions, in small cost. 

There are two or more ADCs inside the MCU. These ADC have excellent sampling rates around 5Msps in this case. There is special modes called "Dual interleaved" mode, where the both ADCs can be used to sample the same channel, With this, sampling rate can be doubles like around 10Msps. That's too great to get in cost of  2.5$ USD.

NOTE: Here you are suggested to use on board DMA for interleaved mode operation