Areas of RTOS

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RTOS concepts
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Why RTOS
Classification of RTOS
- hard real time
 - firm real time
- soft real time

RTOS Architecture

1. Kernel
• what does it do?
• process - ready, running, blocked, suspended (Scheduler)
• process priority
• process communication
• memory management
• provide interfaces for UserSpace applications
• interrupt and event handling
• device io and device driver
• file system
• POSIX
• kernel Types
• monolithic (Most OS like Ubuntu kernel)
• microkernel (Most RTOS like QNX)
• exokernel
2. Scheduler
• First in first out
• Earliest deadline first
• Pre-emptive (Fixed priority)
• Round robin
3. Task
• states - Ready, running, Blocked, Suspended
• Task control block (ID, Priority, Status, register, PC, SP)
• priority of task
• task implementation - creation, deletion, suspend, resume
• idle task
4. Co-routines
• states - ready, Running, Blocked
5. Task synchronization
• Binary semaphore
• Counting semaphore
• Mutex (Mutually Exclusion Semaphores)
• Priority Inversion problem
• Solution - 
• Priority Inheritance
• Priority ceiling
• Recursive mutex
• Task notifications
6. Intertestk communication
• Messgae queues (structured data exchnage )
• Mailbox - messgae queue with length 1
• 
  
• Pipes (unstructured data exchange - byte stream)
• Remote procedure calls (RPC) - one task initiating another task on remote computer. XMLRPC is a kind of RPC as used in project
7. Memory Management
• Stack management
• Heap management
8. Timer Management
• Ticks counting used for task delay
• Task alert
9. Interrupt and Event Handling
• defining Interrupt handler
• creation and deletion of ISR
• Enabling and disabling ISR
• changing and referencing of interrupt mask
10. Device I/O Management
• Provide APIs of using device drivers
11. Selection of RTOS
• Technical consideration
• Scalability
• Portability
• Run-time facilities
• Development tools
• Commercial Considerations
• Costs
• License
• Supplier stability/ longevity
• Usually there are no thread concepts in RTOS. Task are the only things.

How and why to use VOLATILE and CONST in embedded C programming ???

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use of volatile
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Its a qualifier.This keyword is especially valuable when you are interacting with hardware peripheral registers and such via memory-mapped I/O.
It is important to use volatile to declare all variables that are shared by asynchronous software entities, which is important in any kind of multithreaded programming.

int volatile g_flag_shared_with_isr;

uint8_t volatile * p_led_reg = (uint8_t *) 0x00080000;

The first example declares a global flag that can be shared between an ISR and some other part of the code (e.g., a background processing loop in main() or an RTOS task) without fear that the compiler will optimize (i.e., “delete”) the code you write to check for asynchronous changes to the flag’s value. It is important to use volatile to declare all variables that are shared by asynchronous software entities, which is important in any kind of multithreaded programming. (Remember, though, that access to global variables shared by tasks or with an ISR must always also be controlled via a mutex or interrupt disable, respectively.)

The second example declares a pointer to a hardware register at a known physical memory address (80000h)–in this case to manipulate the state of one or more LEDs. Because the pointer to the hardware register is declared volatile, the compiler must always perform each individual write. Even if you write C code to turn an LED on followed immediately by code to turn the same LED off, you can trust that the hardware really will receive both instructions. Because of the sequence point restrictions, you are also guaranteed that the LED will be off after both lines of the C code have been executed. The volatile keyword should always be used with creating pointers to memory-mapped I/O such as this.

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use of const
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uint16_t const max_temp_in_c = 1000;

In C, this variable will exist in memory at run-time, but will typically be located, by the linker, in a non-volatile memory area such as ROM or flash.
Any reference to the const variable will read from that location.

Another use of const is to mark a hardware register as read-only. For example:

uint8_t const * p_latch_reg = 0x10000000;

Declaring the pointer this way, any attempt to write to that physical memory address via the pointer (e.g., *p_latch_reg = 0xFF;) should result in a compile-time error.

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use of volatile and const
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1. Constant Addresses of (Read or Write) Hardware Registers

uint8_t volatile * const p_led_reg = (uint8_t *) 0x00080000;

p_led_reg IS A constant pointer TO A volatile 8-bit unsigned integer. This makes sure that p_led_reg contains address that will never change. Gives us surity that it will always point to same address every time. Typo mistake will not cause any undesired change to value at some different address.



2. Read-Only Shared-Memory Buffer

Another use for a combination of const and volatile is where you have two processors communicating via a shared memory area and you are coding the side of this communications that will only be reading from a shared memory buffer. In this case you could declare variables such as:

int const volatile comm_flag;

uint8_t const volatile comm_buffer[BUFFER_SIZE];


3. (Read-Only) Hardware Register

Sometimes you will run across a read-only hardware register. In addition to enforcing compile-time checking so that the software doesn’t try to overwrite the memory location, you also need to be sure that each and every requested read actually occurs. By declaring your variable IS A (constant) pointer TO A constant and volatile memory location you request all of the appropriate protections, as in:

uint8_t const volatile * const p_latch_reg = (uint8_t *) 0x10000000;

As you can see, the declarations of variables that involve both the volatile and const decorators can quickly become complicated to read. But the technique of combining C’s volatile and const keywords can be useful and even important. This is definitely something you should learn to master to be a master embedded software engineer.

Parallel programming for CPU and GPU

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CPU Parallel programming in C
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POSIX - pthread in linux eg. $gcc -o go go.c -lpthread
OpenMP <omp.h> eg. $gcc -fopenmp -o go go.c
MPI - message passing interface <mpi.h> eg. $mpicc go_mpi.c -o go_mpi
   $mpirun -n 4 go_mpi
   $time mpirun -n 1 go OR $time mpirun -n 4 go

reference link: http://gribblelab.org/CBootcamp/A2_Parallel_Programming_in_C.html

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GPU Parallel programming in C
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OpenCL <cl.h>

Harvard and Von Neumann: Memory Architecture's

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Harvard architecture

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1. Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. Execution difference: Here, decode instruction and execute instruction can be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> execute -> store

Eg. Atmel AVR, Michochip PIC, Intel 8051,



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Modified harvard architecture

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1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. But the memory map is common for both.
3. Usually used in ARM processors
4. There is Instruction cache and Data cache inside the CPU. Even though CODE and DATA memories have separate buses, they are accessed by CPU from I and D cache, one after another. Hence single memory map.

Eg. ARM architecture based any processor and controller

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Von-neumann architecture

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1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. Execution difference: Here, decode instruction and execute instruction cannot be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> evaluate address of operands -> get the operands from memory -> execute ->store

Eg. Texas Instruments MSP430





* Usually External EEPROM is connected to CPU using I2C (or any other communication protocol). EEPROM is treated as a peripheral.
* NAND/NOR FLASH or RAM are connected to CPU using high speed bus AMBA/AHBA. These bus run almost as fast as CPU speed.
* USB and Ethernet as also connected AMBA/AHBA as they are treated as high speed peripherals.
* DMA comes into picture when handling data related to data transfer on USB / Ethernet kind of things. This helps CPU to concentrate on some other task rather than spending time on data transfer kind of tasks.
* Remaining all peripherals are connected using PBA bus which is a low speed bus.

Mixed signal MCU mean's Digital and Analog Circuit on same die.