Harvard and Von Neumann: Memory Architecture's

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Harvard architecture

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1. Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. Execution difference: Here, decode instruction and execute instruction can be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> execute -> store

Eg. Atmel AVR, Michochip PIC, Intel 8051,



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Modified harvard architecture

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1.Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. But the memory map is common for both.
3. Usually used in ARM processors
4. There is Instruction cache and Data cache inside the CPU. Even though CODE and DATA memories have separate buses, they are accessed by CPU from I and D cache, one after another. Hence single memory map.

Eg. ARM architecture based any processor and controller

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Von-neumann architecture

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1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. Execution difference: Here, decode instruction and execute instruction cannot be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> evaluate address of operands -> get the operands from memory -> execute ->store

Eg. Texas Instruments MSP430





* Usually External EEPROM is connected to CPU using I2C (or any other communication protocol). EEPROM is treated as a peripheral.
* NAND/NOR FLASH or RAM are connected to CPU using high speed bus AMBA/AHBA. These bus run almost as fast as CPU speed.
* USB and Ethernet as also connected AMBA/AHBA as they are treated as high speed peripherals.
* DMA comes into picture when handling data related to data transfer on USB / Ethernet kind of things. This helps CPU to concentrate on some other task rather than spending time on data transfer kind of tasks.
* Remaining all peripherals are connected using PBA bus which is a low speed bus.

Mixed signal MCU mean's Digital and Analog Circuit on same die.