Harvard and Von Neumann: Memory Architecture's

--------------------

Harvard architecture

--------------------
1. Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. Execution difference: Here, decode instruction and execute instruction can be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> execute -> store

Eg. Atmel AVR, Michochip PIC, Intel 8051,



--------------------

Modified harvard architecture

--------------------
1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. But the memory map is common for both.
3. Usually used in ARM processors
4. There is Instruction cache and Data cache inside the CPU. Even though CODE and DATA memories have separate buses, they are accessed by CPU from I and D cache, one after another. Hence single memory map.

Eg. ARM architecture based any processor and controller

--------------------

Von-neumann architecture

--------------------
1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. Execution difference: Here, decode instruction and execute instruction cannot be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> evaluate address of operands -> get the operands from memory -> execute ->store

Eg. Texas Instruments MSP430





* Usually External EEPROM is connected to CPU using I2C (or any other communication protocol). EEPROM is treated as a peripheral.
* NAND/NOR FLASH or RAM are connected to CPU using high speed bus AMBA/AHBA. These bus run almost as fast as CPU speed.
* USB and Ethernet as also connected AMBA/AHBA as they are treated as high speed peripherals.
* DMA comes into picture when handling data related to data transfer on USB / Ethernet kind of things. This helps CPU to concentrate on some other task rather than spending time on data transfer kind of tasks.
* Remaining all peripherals are connected using PBA bus which is a low speed bus.

Mixed signal MCU mean's Digital and Analog Circuit on same die.

Some info on CACHE

When considering Harvard architecture, as there are separate Instruction and Data memories, cache are also different.
-Instruction cache (i-cache)
-Data cache (d-cache)

Data cache has a hierarchy (L1, L2, L3 or L4)

In a multicore processor system, L1, L2 cache are independent to each core. Usually the data on L3 and L4 are used for cache sharing between cores.
L1 and L2 cache are not shared as it would result in increase of wiring on silicon and eventually teh size of chip. Shaing L1,L2 cache even makes processing slow as the hit rate in cache decreases.

EXAMPLE:
--------
one classic example is to iterate a multidimensional array "inside out":

pseudocode
for (i = 0 to size)
  for (j = 0 to size)
    do something with ary[j][i]
The reason this is cache inefficient is because modern CPUs will load the cache line with "near" memory addresses from main memory when you access a single memory address. We are iterating through the "j" (outer) rows in the array in the inner loop, so for each trip through the inner loop, the cache line will cause to be flushed and loaded with a line of addresses that are near to the [j][i] entry. If this is changed to the equivalent:

for (i = 0 to size)
  for (j = 0 to size)
    do something with ary[i][j]
It will run much faster.

Harvard and Von Neumann: Memory Architecture's

--------------------

Harvard architecture

--------------------
1. Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. Execution difference: Here, decode instruction and execute instruction can be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> execute -> store

Eg. Atmel AVR, Michochip PIC, Intel 8051,



--------------------

Modified harvard architecture

--------------------
1.Physical connection
ROM(Program memory) <---Addr and Data Buses------> CPU <---Addr and Data Buses------> RAM(Data memory)

2. But the memory map is common for both.
3. Usually used in ARM processors
4. There is Instruction cache and Data cache inside the CPU. Even though CODE and DATA memories have separate buses, they are accessed by CPU from I and D cache, one after another. Hence single memory map.

Eg. ARM architecture based any processor and controller

--------------------

Von-neumann architecture

--------------------
1.Physical connection
ROM(Program memory) & RAM(Data memory) <---Addr and Data Buses------> CPU

2. Execution difference: Here, decode instruction and execute instruction cannot be done one after another.
3. Following are the instruction execution steps:
fetch -> decode -> evaluate address of operands -> get the operands from memory -> execute ->store

Eg. Texas Instruments MSP430





* Usually External EEPROM is connected to CPU using I2C (or any other communication protocol). EEPROM is treated as a peripheral.
* NAND/NOR FLASH or RAM are connected to CPU using high speed bus AMBA/AHBA. These bus run almost as fast as CPU speed.
* USB and Ethernet as also connected AMBA/AHBA as they are treated as high speed peripherals.
* DMA comes into picture when handling data related to data transfer on USB / Ethernet kind of things. This helps CPU to concentrate on some other task rather than spending time on data transfer kind of tasks.
* Remaining all peripherals are connected using PBA bus which is a low speed bus.

Mixed signal MCU mean's Digital and Analog Circuit on same die.

MCIROCODES and its significance...

Microcodes are something that is present in control unit section of CPU. It resides in control store part of i.e. like a high speed ROM in control unit of CPU.
Control unit decodes instruction from code and call the particular instruction of microcode.
Microinstruction from microcode are large in size like around 50bit or more... because they generate the required signals based on its each bit to ALU.

Microcodes system is only used in CISC based architectures. It is used instead of hardwire circuit bcz, it reduces the job of designing complex "control unit" circuit in CISC.

RISC uses Hardwired control unit circuit. Previously, the job of writing assembly code for RISC processor was time consuming as it required LOAD and STORE instruction for every simple job like "Addition  of two numbers"
RISC architecture assembly code takes more space on RAM as compared to CISC.

But as years passed, the compilers became so improved that, no more assembly level programming is mandatory. Hence, in RISC architecture based system, more emphasis is given on software side i.e. more emphasis given on building intelligent compiler.